----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:52:19 01/29/2011 
-- Design Name: 
-- Module Name:    MAIN_CONTROtop - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.LCSE.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MAIN_CONTROtop is
Port( 
	Reset     : in  std_logic;
   Clk       : in  std_logic;
   --ROM_Data  : in  std_logic_vector(11 downto 0);
   --ROM_Addr  : out  std_logic_vector(11 downto 0);
   RAM_Addr  : out  std_logic_vector(7 downto 0);   
   RAM_CS    : out  std_logic;
   RAM_Write : out  std_logic;
   RAM_OE    : out  std_logic;
   DMA_RQ    : in  std_logic;
   DMA_ACK   : out  std_logic;
   SEND_comm : out  std_logic;
   DMA_READY : in  std_logic
--   i_Databus   : in  std_logic_vector(7 downto 0);			
--   i_Databus_OE   : in  std_logic_vector(7 downto 0);			
--   o_Databus   : out  std_logic_vector(7 downto 0)			
);
end MAIN_CONTROtop;

architecture Behav of MAIN_CONTROtop is

----------------------------------------------------
------Component for ROM
----------------------------------------------------
component ROM
	port(
			Instruction     : out std_logic_vector(11 downto 0);  -- Instruction bus
			Program_counter : in  std_logic_vector(11 downto 0)--data bus of ROM
		 );
end component;

------------------------------------------------------
----component for main_control
------------------------------------------------------
component MAIN_CONTROL
	port(
			  Reset : in  STD_LOGIC;
           Clk   : in  STD_LOGIC;
           --------ROM---------------------------------------
			  ROM_Data : in  STD_LOGIC_VECTOR (11 downto 0); --data bus program memory
           ROM_Addr : out  STD_LOGIC_VECTOR (11 downto 0);--written by main control--address bus program memory
           -----RAM------------------------------------------
			  RAM_Addr : out  STD_LOGIC_vector(7 downto 0);--written by main control--adress bus of data memory
			  RAM_CS : out  STD_LOGIC;--by main control
           RAM_Write : out  STD_LOGIC;--written by main control
           RAM_OE : out  STD_LOGIC;--written by main control
           -------DMA------------------------------------
			  Databus : inout  STD_LOGIC_vector(7 downto 0);
           DMA_RQ : in  STD_LOGIC;--from the DMA controler
           DMA_ACK : out  STD_LOGIC;--written by main control
           SEND_comm : out  STD_LOGIC;--written by main control--transmission of data 
           DMA_READY : in  STD_LOGIC;--from the DMA controller
			 --------ALU---------------------------------
			  u_instruction : out alu_op;
			  Index: in std_logic_vector(7 downto 0);
			 --Flags--------------------------------------
           FlagZ : in  STD_LOGIC;
           FlagC : in  STD_LOGIC;
           FlagN : in  STD_LOGIC;
           FlagE : in  STD_LOGIC
			  );
			  
		end component;

----------------------------------------------------
------Component for ALU
----------------------------------------------------

 component ALU
	port(
			Reset : in std_logic;
			Clk : in std_logic;
			u_instruction : in alu_op;-- U-instruction from the cpu
			FlagC : out std_logic;--carry flag
			FlagZ : out std_logic;--Zero flag
			FlagN : out std_logic;--carry bit Nibble flag
			FlagE : out std_logic;--error flag
			Databus: inout std_logic_vector(7 downto 0);
			Index_Reg: out std_logic_vector(7 downto 0)--index register
			);
	end component;

--------Internal Signals---------------------------------------------

signal FlagZ:STD_LOGIC;
signal FlagC : STD_LOGIC;
signal FlagN :STD_LOGIC;
signal FlagE : STD_LOGIC;
------------------------------------------------------------- 
signal alu_op_s:alu_op; 
signal Index_reg: std_logic_vector(7 downto 0);

---internal registers---------------
signal Instruction     : std_logic_vector(11 downto 0); -- Instruction bus
signal Program_counter : std_logic_vector(11 downto 0); --written by main control
----------------------------------------------------------------------
signal Databus: std_logic_vector(7 downto 0);
begin

-- o_Databus <= Databus;
-- Databus <= i_Databus WHEN i_Databus_OE='1' ELSE (others => 'Z');

arith: ALU
port map(
			Reset=> Reset,           
			Clk => Clk,
			u_instruction=> alu_op_s, -- U-instruction from the cpu
			FlagC=> FlagC,
			FlagZ=> FlagZ,
			FlagN=> FlagN,--carry bit Nibble flag
			FlagE=> FlagE,
			Databus=> Databus,
			Index_Reg=>Index_Reg 
			);
			
------------------------------------------------------------------------------------

AUTOMATIC:ROM
 port map(
				Program_counter=> Program_counter,  --address bus of ROM
				Instruction  => Instruction);

---------------------------------------------

Main_cont:MAIN_CONTROL
	port map(	
			  Reset=> Reset,
           Clk=>Clk,
           --------ROM---------------------------------------
			  ROM_Data =>Instruction, --data bus program memory
           ROM_Addr=>Program_counter,--written by main control--address bus program memory
           -----RAM------------------------------------------
			  RAM_Addr=>RAM_Addr,--written by main control--adress bus of data memory
			  RAM_CS=>RAM_CS,
           RAM_Write=>RAM_Write,--written by main control
           RAM_OE=>RAM_OE,--written by main control
           -------DMA-----------------------------------
			  Databus=>Databus,
           DMA_RQ=>DMA_RQ,--from the DMA controler
           DMA_ACK=>DMA_ACK,--written by main control
           SEND_comm=>SEND_comm,--written by main control--transmission of data 
           DMA_READY=>DMA_READY,--from the DMA controller
           -------ALU----------------------------------
			  u_instruction=>alu_op_s, 
			  Index=>Index_reg,
           FlagZ=>FlagZ,
           FlagC=>FlagC,
           FlagN=>FlagN,
           FlagE=>FlagE 
			  );
end Behav;


















